/**
	*****************************************************************************
	* @file     cmem7_adc.h
	*
	* @brief    CMEM7 ADC header file
	*
	*
	* @version  V1.0
	* @date     3. September 2013
	*
	* @note               
	*           
	*****************************************************************************
	* @attention
	*
	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
	*
	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
	*****************************************************************************
	*/
	
#ifndef __CMEM7_ADC_H
#define __CMEM7_ADC_H

#ifdef __cplusplus
 extern "C" {
#endif

#include "cmem7.h"
#include "cmem7_conf.h"

typedef enum {
	ADC_PERIPH_1,
	ADC_PERIPH_2,
} ADC_PERIPH;

#define IS_ADC_ALL_PERIPH(PERIPH)         (((PERIPH) == ADC_PERIPH_1) || \
                                           ((PERIPH) == ADC_PERIPH_2))

#define ADC_VSEN_VDDCORE                  1
#define ADC_VSEN_VDDIO                    2
#define ADC_VSEN_VDDIO2                   4

#define IS_ADC_VSEN(VSEN)                 (((VSEN) == ADC_VSEN_VDDCORE) || \
                                           ((VSEN) == ADC_VSEN_VDDIO) || \
                                           ((VSEN) == ADC_VSEN_VDDIO2))

#define ADC_PHASE_CTRL_0DEG_RISE_EDGE     0         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */                                               
#define ADC_PHASE_CTRL_90DEG_AHEAD        1         /* ADC-1 90DEG ahead of ADC-2 */
#define ADC_PHASE_CTRL_90DEG_LAG          2         /* ADC-1 90DEG lag of ADC-2 */
#define ADC_PHASE_CTRL_0DEG_FALL_EDGE     3         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */

#define IS_ADC_PHASE_CTRL(CTRL)           (((CTRL) == ADC_PHASE_CTRL_0DEG_RISE_EDGE) || \
                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_AHEAD) || \
                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_LAG) || \
                                           ((CTRL) == ADC_PHASE_CTRL_0DEG_FALL_EDGE))
																					 
#define ADC_CALIBRATION_OFFSET            3
#define ADC_CALIBRATION_NEGTIVE_GAIN      4
#define ADC_CALIBRATION_POSTIVE_GAIN      5

#define IS_ADC_CALIBRATION(CALIB)         (((CALIB) == ADC_CALIBRATION_OFFSET) || \
                                           ((CALIB) == ADC_CALIBRATION_NEGTIVE_GAIN) || \
                                           ((CALIB) == ADC_CALIBRATION_POSTIVE_GAIN))
																					 
#define ADC1_CHANNEL_VIP                  0		
#define ADC1_CHANNEL_VSEN                 1
#define ADC1_CHANNEL_VTMP                 2
#define ADC1_CHANNEL_VADIO_0              3
#define ADC1_CHANNEL_VADIO_1              4
#define ADC1_CHANNEL_VADIO_2              5
#define ADC1_CHANNEL_VADIO_3              6
#define ADC1_CHANNEL_VADIO_4              7

#define IS_ADC1_CHANNEL(CHANNEL)          (((CHANNEL) == ADC1_CHANNEL_VIP) || \
                                           ((CHANNEL) == ADC1_CHANNEL_VSEN) || \
                                           ((CHANNEL) == ADC1_CHANNEL_VTMP) || \
																					 ((CHANNEL) == ADC1_CHANNEL_VADIO_0) || \
																					 ((CHANNEL) == ADC1_CHANNEL_VADIO_1) || \
																					 ((CHANNEL) == ADC1_CHANNEL_VADIO_2) || \
																					 ((CHANNEL) == ADC1_CHANNEL_VADIO_3) || \
                                           ((CHANNEL) == ADC1_CHANNEL_VADIO_4))
																					 
#define ADC2_CHANNEL_VIN                  0		
#define ADC2_CHANNEL_VADIO_5              1
#define ADC2_CHANNEL_VADIO_6              2
#define ADC2_CHANNEL_VADIO_7              3
#define ADC2_CHANNEL_VADIO_8              4
#define ADC2_CHANNEL_VADIO_9              5
#define ADC2_CHANNEL_VADIO_10             6
#define ADC2_CHANNEL_VADIO_11             7

#define IS_ADC2_CHANNEL(CHANNEL)          (((CHANNEL) == ADC2_CHANNEL_VIN) || \
                                           ((CHANNEL) == ADC2_CHANNEL_VADIO_5) || \
                                           ((CHANNEL) == ADC2_CHANNEL_VADIO_6) || \
																					 ((CHANNEL) == ADC2_CHANNEL_VADIO_7) || \
																					 ((CHANNEL) == ADC2_CHANNEL_VADIO_8) || \
																					 ((CHANNEL) == ADC2_CHANNEL_VADIO_9) || \
																					 ((CHANNEL) == ADC2_CHANNEL_VADIO_10) || \
                                           ((CHANNEL) == ADC2_CHANNEL_VADIO_11))																					 
																					 

typedef struct
{
	uint8_t ADC_PhaseCtrl;                  /*!< Phase between ADC1 and ADC2                    */
  uint8_t ADC_VsenSelection;              /*!< ADC VSENS selection                            */
} ADC_InitTypeDef;

void ADC_Init(ADC_InitTypeDef* init);
/* It takes 1ms or 8ms if enable is false or true respectively */
void ADC_Enable(uint8_t adc, BOOL enable);
/* continuous conversion if convNum is 0 */
BOOL ADC_StartConversion(uint8_t adc, uint8_t channel, uint8_t convNum);
BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration);
/* return value is actual read data size */
uint8_t ADC_Read(uint8_t adc, uint8_t size, uint16_t* data);

#ifdef __cplusplus
}
#endif

#endif /*__CMEM7_ADC_H */

